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1

[Frontiers in Electronic Testing] Timing Performance of Nanometer Digital Circuits Under Process Variations Volume 39 || Designing with FinFETs and Process Variation Impact

Champac, Victor, Garcia Gervacio, Jose

Year:

2018

Language:

english

File:

PDF, 1.45 MB

english, 2018

2

Delay sensing for long-term variations and defects monitoring in safety–critical applications

J. C. Vazquez, V. Champac, A. M. Ziesemer, R. Reis, I. C. Teixeira, M. B. Santos, J. P. Teixeira

Journal:

Analog Integrated Circuits and Signal Processing

Year:

2012

Language:

english

File:

PDF, 1.03 MB

english, 2012

3

[IEEE 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008 - Seattle, WA, USA (2008.05.18-2008.05.21)] 2008 IEEE International Symposium on Circuits and Systems - A design methodology for logic paths tolerant to local intra-die variations

Iparraguirre-Cardenas, Daniel, Garcia-Gervacio, Jose L., Champac, Victor

Year:

2008

Language:

english

File:

PDF, 198 KB

english, 2008

4

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - The noise immunity of dynamic digital circuits with technology scaling

Mendoza-Hernandez, F., Linares, M., Champac, V.H.

Year:

2004

Language:

english

File:

PDF, 288 KB

english, 2004

5

[IEEE 2002 IEEE International Symposium on Circuits and Systems - Phoenix-Scottsdale, AZ, USA (26-29 May 2002)] 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) - A new technique for noise-tolerant pipelined dynamic digital circuits

Mendoza-Hernandez, F., Linares, M., Champac, V.H., Diaz-Sanchez, A.

Year:

2002

Language:

english

File:

PDF, 293 KB

english, 2002

6

Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring

Gomez, Andres F., Champac, Victor

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2016

Language:

english

File:

PDF, 2.71 MB

english, 2016

7

[IEEE 1991, International Test Conference - Nashville, TN (Oct. 26-30 1991)] 1991, Proceedings. International Test Conference - CURRENT VS. LOGIC TESTING OF GATE OXIDE SHORT, FLOATING GATE AND BRIDGING FAILURES IN CMOS

Rodriguez-Montanes, R., Segura, J.A., Champac, V.H., Figueras, J., Rubio, J.A.

Year:

1991

Language:

english

File:

PDF, 827 KB

english, 1991

8

Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test

Hector Villacorta, Victor Champac, Sebastià Bota, Jaume Segura

Journal:

Microelectronics Reliability

Year:

2012

Language:

english

File:

PDF, 858 KB

english, 2012

9

Screening small-delay defects using inter-path correlation to reduce reliability risk

García-Gervacio, José L., Nocua, Alejandro, Champac, Victor

Journal:

Microelectronics Reliability

Year:

2015

Language:

english

File:

PDF, 1.51 MB

english, 2015

10

Testing of Stuck-Open Faults in Nanometer Technologies

Champac, Victor, Vazquez Hernandez, Julio, Barcelo, Salvador, Gomez, Roberto, Hawkins, Chuck, Segura, Jaume

Journal:

IEEE Design & Test of Computers

Year:

2012

Language:

english

File:

PDF, 1003 KB

english, 2012

11

Gate Sizing Methodology with a Novel Accurate Metric to Improve Circuit Timing Performance under Process Variations

Perez-Rivera, Zahira, Tlelo-Cuautle, Esteban, Champac, Victor

Journal:

Year:

2020

File:

PDF, 1.08 MB

2020

12

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - An improved technique to increase noise-tolerance in dynamic digital circuits

Mendoza-Hernandez, F., Linares, M., Champac, V.H.

Year:

2004

Language:

english

File:

PDF, 294 KB

english, 2004

13

An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects

Gomez, Andres, Champac, Victor

Journal:

Journal of Electronic Testing

Year:

2019

File:

PDF, 1.48 MB

2019

14

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Champac, V., Avendano, V., Figueras, J.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2010

Language:

english

File:

PDF, 1.13 MB

english, 2010

15

[IEEE 2019 IEEE Latin American Test Symposium (LATS) - Santiago, Chile (2019.3.11-2019.3.13)] 2019 IEEE Latin American Test Symposium (LATS) - A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells

Forero, Freddy, Galliere, Jean-Marc, Renovell, Michel, Champac, Victor

Year:

2019

Language:

english

File:

PDF, 826 KB

english, 2019

16

[IEEE 2019 IEEE Latin American Test Symposium (LATS) - Santiago, Chile (2019.3.11-2019.3.13)] 2019 IEEE Latin American Test Symposium (LATS) - Identification of Logic Paths Influenced by Severe Coupling Capacitances

Meza-Ibarra, I. D., Champac, V., Gomez-Fuentes, R., Noriega, J. R., Vera-Marquina, A.

Year:

2019

Language:

english

File:

PDF, 112 KB

english, 2019

17

IDDQ Testing of Opens in CMOS SRAMs

Victor H. Champac, José Castillejos, Joan Figueras

Journal:

Journal of Electronic Testing

Year:

1999

Language:

english

File:

PDF, 79 KB

english, 1999

18

[IEEE 2014 IEEE 32nd VLSI Test Symposium (VTS) - Napa, CA, USA (2014.04.13-2014.04.17)] 2014 IEEE 32nd VLSI Test Symposium (VTS) - Hot topic session 12B: Stay relevant with standards-based DFT

Clark, C J, Champac, Victor

Year:

2014

Language:

english

File:

PDF, 107 KB

english, 2014

19

[IEEE 2009 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) - Cancun, Mexico (2009.08.2-2009.08.5)] 2009 52nd IEEE International Midwest Symposium on Circuits and Systems - A methodology to compute the statistical fault coverage of small delays due to opens

Garcia-Gervacio, Jose L., Champac, Victor

Year:

2009

Language:

english

File:

PDF, 575 KB

english, 2009

20

[IEEE Comput. Soc. Press [1992] The European Conference on Design Automation - Brussels, Belgium (16-19 March 1992)] [1992] Proceedings The European Conference on Design Automation - Quiescent current estimation for current testing

Balado, L., Figueras, J., Rubio, J.A., Champac, V., Rodriguez, R., Segura, J.

Year:

1992

Language:

english

File:

PDF, 441 KB

english, 1992

21

[IEEE 2016 17th Latin-American Test Symposium (LATS) - Foz do Iguacu, Brazil (2016.4.6-2016.4.8)] 2016 17th Latin-American Test Symposium (LATS) - A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage

Forero, Freddy, Gomez, Andres, Champac, Victor

Year:

2016

Language:

english

File:

PDF, 2.49 MB

english, 2016

22

CGTDEMO --- educational software for the central limit theorem

Jovanovic-Dolecek, Gordana, Champac, Victor H.

Journal:

ACM SIGCSE Bulletin

Year:

2000

Language:

english

File:

PDF, 288 KB

english, 2000

23

[IEEE Comput. Soc 19th IEEE VLSI Test Symposium. VTS 2001 - Marina Del Rey, CA, USA (29 April-3 May 2001)] Proceedings 19th IEEE VLSI Test Symposium. VTS 2001 - Resistive opens in a class of CMOS latches: analysis and DFT

Zenteno, A., Champac, V.H.

Year:

2001

Language:

english

File:

PDF, 509 KB

english, 2001

24

[IEEE 2015 16th Latin-American Test Symposium (LATS) - Puerto Vallarta, Mexico (2015.3.25-2015.3.27)] 2015 16th Latin-American Test Symposium (LATS) - Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell

Villacorta, Hector, Gomez, Roberto, Bota, Sebastia, Segura, Jaume, Champac, Victor

Year:

2015

Language:

english

File:

PDF, 1.34 MB

english, 2015

25

[IEEE 2018 IEEE 19th Latin-American Test Symposium (LATS) - Sao Paulo, Brazil (2018.3.12-2018.3.14)] 2018 IEEE 19th Latin-American Test Symposium (LATS) - A metric-guided gate-sizing methodology for aging guardband reduction

Gomez, Andres F., Gomez, Roberto, Champac, Victor

Year:

2018

Language:

english

File:

PDF, 901 KB

english, 2018

26

[IEEE 2010 28th VLSI Test Symposium (VTS) - Santa Cruz, CA, USA (2010.04.19-2010.04.22)] 2010 28th VLSI Test Symposium (VTS) - Low-sensitivity to process variations aging sensor for automotive safety-critical applications

Vazquez, J. C., Champac, V., Ziesemer, A. M., Reis, R., Teixeira, I. C., Santos, M. B., Teixeira, J. P.

Year:

2010

Language:

english

File:

PDF, 858 KB

english, 2010

27

[IEEE 2008 IEEE Computer Society Annual Symposium on VLSI - Montpellier, France (2008.04.7-2008.04.9)] 2008 IEEE Computer Society Annual Symposium on VLSI - Testing Skew and Logic Faults in SoC Interconnects

Hernández, Néstor, Champac, Victor

Year:

2008

Language:

english

File:

PDF, 1.53 MB

english, 2008

28

Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability

Villacorta, Hector, Segura, Jaume, Champac, Victor

Journal:

Journal of Electronic Testing

Year:

2016

Language:

english

File:

PDF, 958 KB

english, 2016

29

Modeling and Detectability of Full Open Gate Defects in FinFET Technology

Forero, Freddy, Villacorta, Hector, Renovell, Michel, Champac, Victor

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2019

Language:

english

File:

PDF, 45 KB

english, 2019

30

Guest Editorial

Fabian Vargas, Victor Champac

Journal:

Journal of Electronic Testing

Year:

2004

Language:

english

File:

PDF, 29 KB

english, 2004

31

Test of data retention faults in CMOS SRAMs using special DFT circuitries

Champac, V.H., Avendano, V.

Journal:

IEE Proceedings - Circuits Devices and Systems

Year:

2004

Language:

english

File:

PDF, 1.39 MB

english, 2004

32

[IEEE 2010 IEEE 16th International On-Line Testing Symposium (IOLTS 2010) - Corfu, Greece (2010.07.5-2010.07.7)] 2010 IEEE 16th International On-Line Testing Symposium - Predictive error detection by on-line aging monitoring

Vazquez, J. C., Champac, V., Ziesemer, A. M., Reis, R., Semiao, J., Teixeira, I. C., Santos, M. B., Teixeira, J. P.

Year:

2010

Language:

english

File:

PDF, 944 KB

english, 2010

33

Noise-tolerance improvement in dynamic CMOS logic circuits

Mendoza-Hernandez, F., Linares-Aranda, M., Champac, V.

Journal:

IEE Proceedings - Circuits Devices and Systems

Year:

2006

Language:

english

File:

PDF, 273 KB

english, 2006

34

[IEEE 2011 IEEE VLSI Test Symposium (VTS) - Dana Point, CA, USA (2011.05.1-2011.05.5)] 29th VLSI Test Symposium - A new methodology for realistic open defect detection probability evaluation under process variations

Moreno, Jesus, Champac, Victor, Renovell, Michel

Year:

2011

Language:

english

File:

PDF, 754 KB

english, 2011

35

[IEEE 2012 13th Latin American Test Workshop - LATW - Quito, Ecuador (2012.04.10-2012.04.13)] 2012 13th Latin American Test Workshop (LATW) - Low voltage testing for interconnect opens under process variations

Moreno, Jesus, Champac, Victor, Renovell, Michel

Year:

2012

Language:

english

File:

PDF, 1.10 MB

english, 2012

36

[IEEE 2009 27th IEEE VLSI Test Symposium (VTS) - Santa Cruz, CA, USA (2009.05.3-2009.05.7)] 2009 27th IEEE VLSI Test Symposium - Stuck-Open Fault Leakage and Testing in Nanometer Technologies

Vazquez, Julio, Champac, Victor, Hawkins, Chuck, Segura, Jaume

Year:

2009

Language:

english

File:

PDF, 1.16 MB

english, 2009

37

[IEEE 2014 15th Latin American Test Workshop - LATW - Fortaleza, Brazil (2014.3.12-2014.3.15)] 2014 15th Latin American Test Workshop - LATW - Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies

Garcia-Gervacio, Jose L., Martinez-Castillo, Jaime, Champac, Victor

Year:

2014

Language:

english

File:

PDF, 171 KB

english, 2014

38

Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations

Moreno, Jesus, Renovell, Michel, Champac, Victor

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2015

Language:

english

File:

PDF, 772 KB

english, 2015

39

IDDQ testing of single floating gate defects using a two-pattern vector

Champac, V.H., Figueras, J.

Journal:

Electronics Letters

Year:

1996

Language:

english

File:

PDF, 69 KB

english, 1996

40

[IEEE 2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS) - Foz do Iguacu, Brazil (2010.2.24-2010.2.26)] 2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS) - A Short-channel silicon-based Split-Drain MAGFET measuring from 90 µT

Santillan-Quinonez, Gerard F., Champac, Victor, Murphy, Roberto S.

Year:

2010

Language:

english

File:

PDF, 1.19 MB

english, 2010

41

[IEEE 2016 IEEE European Test Symposium (ETS) - Amsterdam, Netherlands (2016.5.23-2016.5.27)] 2016 21th IEEE European Test Symposium (ETS) - Behavior and test of open-gate defects in FinFET based cells

Mesalles, F., Villacorta, H., Renovell, M., Champac, V.

Year:

2016

Language:

english

File:

PDF, 1.69 MB

english, 2016

42

Exploiting magnetic sensing capabilities of Short Split-Drain MAGFETs

Gerard F. Santillan-Quiñonez, Victor Champac, Roberto S. Murphy

Journal:

Solid-State Electronics

Year:

2010

Language:

english

File:

PDF, 843 KB

english, 2010

43

[IEEE Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. - Corsica, France (23-26 May 2004)] Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. - Signal integrity verification using high speed monitors

Avendano, V., Champac, V., Figueras, J.

Year:

2004

Language:

english

File:

PDF, 674 KB

english, 2004

44

Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects

Gomez, Andres F., Champac, Victor

Journal:

ACM Transactions on Design Automation of Electronic Systems

Year:

2018

Language:

english

File:

PDF, 2.86 MB

english, 2018

45

Detectability Conditions of Full Opens in the Interconnections

Antonio Zenteno, Victor H. Champac, Joan Figueras

Journal:

Journal of Electronic Testing

Year:

2001

Language:

english

File:

PDF, 491 KB

english, 2001

46

Low VDD and body bias conditions for testing bridge defects in the presence of process variations

Villacorta, Hector, Garcia-Gervacio, Jose, Segura, Jaume, Champac, Victor

Journal:

Microelectronics Journal

Year:

2015

Language:

english

File:

PDF, 541 KB

english, 2015

47

Detectability Challenges of Bridge Defects in FinFET Based Logic Cells

Forero, Freddy, Galliere, Jean-Marc, Renovell, Michel, Champac, Victor

Journal:

Journal of Electronic Testing

Year:

2018

Language:

english

File:

PDF, 1.43 MB

english, 2018

48

Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing

Champac, V.H., Rubio, A., Figueras, J.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

1994

Language:

english

File:

PDF, 1.02 MB

english, 1994

49

[IEEE 2011 IEEE VLSI Test Symposium (VTS) - Dana Point, CA, USA (2011.05.1-2011.05.5)] 29th VLSI Test Symposium - Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors

Martins, C. V., Semiao, J., Vazquez, J. C., Champac, V., Santos, M., Teixeira, I. C., Teixeira, J. P.

Year:

2011

Language:

english

File:

PDF, 981 KB

english, 2011

50

[IEEE 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems - Cancun, Mexico (15-17 March 2000)] Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) - Switching noise due to internal gates: delay implications and modeling

Casimiro Gomez, G., Cadena, A., Champac, V.H.

Year:

2000

Language:

english

File:

PDF, 292 KB

english, 2000

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